    IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC
INCLUDED_CYFITTERRV_INC EQU 1
    GET cydevicerv.inc
    GET cydevicerv_trm.inc

; UART_BUART
UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
UART_BUART_sRX_RxBitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
UART_BUART_sRX_RxBitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
UART_BUART_sRX_RxBitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
UART_BUART_sRX_RxBitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
UART_BUART_sRX_RxBitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
UART_BUART_sRX_RxBitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
UART_BUART_sRX_RxBitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
UART_BUART_sRX_RxBitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
UART_BUART_sRX_RxBitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
UART_BUART_sRX_RxBitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
UART_BUART_sRX_RxBitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
UART_BUART_sRX_RxBitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
UART_BUART_sRX_RxBitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
UART_BUART_sRX_RxBitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
UART_BUART_sRX_RxBitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
UART_BUART_sRX_RxBitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
UART_BUART_sRX_RxBitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
UART_BUART_sRX_RxBitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
UART_BUART_sRX_RxBitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
UART_BUART_sRX_RxShifter_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
UART_BUART_sRX_RxShifter_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
UART_BUART_sRX_RxShifter_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
UART_BUART_sRX_RxShifter_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
UART_BUART_sRX_RxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
UART_BUART_sRX_RxShifter_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
UART_BUART_sRX_RxShifter_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
UART_BUART_sRX_RxShifter_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
UART_BUART_sRX_RxShifter_u0__A0_REG EQU CYREG_B1_UDB04_A0
UART_BUART_sRX_RxShifter_u0__A1_REG EQU CYREG_B1_UDB04_A1
UART_BUART_sRX_RxShifter_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
UART_BUART_sRX_RxShifter_u0__D0_REG EQU CYREG_B1_UDB04_D0
UART_BUART_sRX_RxShifter_u0__D1_REG EQU CYREG_B1_UDB04_D1
UART_BUART_sRX_RxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
UART_BUART_sRX_RxShifter_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
UART_BUART_sRX_RxShifter_u0__F0_REG EQU CYREG_B1_UDB04_F0
UART_BUART_sRX_RxShifter_u0__F1_REG EQU CYREG_B1_UDB04_F1
UART_BUART_sRX_RxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
UART_BUART_sRX_RxSts__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
UART_BUART_sRX_RxSts__3__MASK EQU 0x08
UART_BUART_sRX_RxSts__3__POS EQU 3
UART_BUART_sRX_RxSts__4__MASK EQU 0x10
UART_BUART_sRX_RxSts__4__POS EQU 4
UART_BUART_sRX_RxSts__5__MASK EQU 0x20
UART_BUART_sRX_RxSts__5__POS EQU 5
UART_BUART_sRX_RxSts__MASK EQU 0x38
UART_BUART_sRX_RxSts__MASK_REG EQU CYREG_B1_UDB04_MSK
UART_BUART_sRX_RxSts__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
UART_BUART_sRX_RxSts__STATUS_REG EQU CYREG_B1_UDB04_ST
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
UART_BUART_sTX_sCLOCK_TxBitClkGen__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
UART_BUART_sTX_sCLOCK_TxBitClkGen__A0_REG EQU CYREG_B0_UDB04_A0
UART_BUART_sTX_sCLOCK_TxBitClkGen__A1_REG EQU CYREG_B0_UDB04_A1
UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
UART_BUART_sTX_sCLOCK_TxBitClkGen__D0_REG EQU CYREG_B0_UDB04_D0
UART_BUART_sTX_sCLOCK_TxBitClkGen__D1_REG EQU CYREG_B0_UDB04_D1
UART_BUART_sTX_sCLOCK_TxBitClkGen__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
UART_BUART_sTX_sCLOCK_TxBitClkGen__F0_REG EQU CYREG_B0_UDB04_F0
UART_BUART_sTX_sCLOCK_TxBitClkGen__F1_REG EQU CYREG_B0_UDB04_F1
UART_BUART_sTX_sCLOCK_TxBitClkGen__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
UART_BUART_sTX_sCLOCK_TxBitClkGen__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
UART_BUART_sTX_TxShifter_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0
UART_BUART_sTX_TxShifter_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1
UART_BUART_sTX_TxShifter_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0
UART_BUART_sTX_TxShifter_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1
UART_BUART_sTX_TxShifter_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
UART_BUART_sTX_TxShifter_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0
UART_BUART_sTX_TxShifter_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1
UART_BUART_sTX_TxShifter_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1
UART_BUART_sTX_TxShifter_u0__A0_REG EQU CYREG_B0_UDB07_A0
UART_BUART_sTX_TxShifter_u0__A1_REG EQU CYREG_B0_UDB07_A1
UART_BUART_sTX_TxShifter_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1
UART_BUART_sTX_TxShifter_u0__D0_REG EQU CYREG_B0_UDB07_D0
UART_BUART_sTX_TxShifter_u0__D1_REG EQU CYREG_B0_UDB07_D1
UART_BUART_sTX_TxShifter_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
UART_BUART_sTX_TxShifter_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1
UART_BUART_sTX_TxShifter_u0__F0_REG EQU CYREG_B0_UDB07_F0
UART_BUART_sTX_TxShifter_u0__F1_REG EQU CYREG_B0_UDB07_F1
UART_BUART_sTX_TxSts__0__MASK EQU 0x01
UART_BUART_sTX_TxSts__0__POS EQU 0
UART_BUART_sTX_TxSts__1__MASK EQU 0x02
UART_BUART_sTX_TxSts__1__POS EQU 1
UART_BUART_sTX_TxSts__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
UART_BUART_sTX_TxSts__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
UART_BUART_sTX_TxSts__2__MASK EQU 0x04
UART_BUART_sTX_TxSts__2__POS EQU 2
UART_BUART_sTX_TxSts__3__MASK EQU 0x08
UART_BUART_sTX_TxSts__3__POS EQU 3
UART_BUART_sTX_TxSts__MASK EQU 0x0F
UART_BUART_sTX_TxSts__MASK_REG EQU CYREG_B0_UDB07_MSK
UART_BUART_sTX_TxSts__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
UART_BUART_sTX_TxSts__STATUS_REG EQU CYREG_B0_UDB07_ST

; UART_RXInternalInterrupt
UART_RXInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
UART_RXInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
UART_RXInternalInterrupt__INTC_MASK EQU 0x01
UART_RXInternalInterrupt__INTC_NUMBER EQU 0
UART_RXInternalInterrupt__INTC_PRIOR_NUM EQU 1
UART_RXInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
UART_RXInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
UART_RXInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; UART_TXInternalInterrupt
UART_TXInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
UART_TXInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
UART_TXInternalInterrupt__INTC_MASK EQU 0x02
UART_TXInternalInterrupt__INTC_NUMBER EQU 1
UART_TXInternalInterrupt__INTC_PRIOR_NUM EQU 5
UART_TXInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
UART_TXInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
UART_TXInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; XRES
XRES__0__MASK EQU 0x10
XRES__0__PC EQU CYREG_PRT12_PC4
XRES__0__PORT EQU 12
XRES__0__SHIFT EQU 4
XRES__AG EQU CYREG_PRT12_AG
XRES__BIE EQU CYREG_PRT12_BIE
XRES__BIT_MASK EQU CYREG_PRT12_BIT_MASK
XRES__BYP EQU CYREG_PRT12_BYP
XRES__DM0 EQU CYREG_PRT12_DM0
XRES__DM1 EQU CYREG_PRT12_DM1
XRES__DM2 EQU CYREG_PRT12_DM2
XRES__DR EQU CYREG_PRT12_DR
XRES__INP_DIS EQU CYREG_PRT12_INP_DIS
XRES__MASK EQU 0x10
XRES__PORT EQU 12
XRES__PRT EQU CYREG_PRT12_PRT
XRES__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
XRES__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
XRES__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
XRES__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
XRES__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
XRES__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
XRES__PS EQU CYREG_PRT12_PS
XRES__SHIFT EQU 4
XRES__SIO_CFG EQU CYREG_PRT12_SIO_CFG
XRES__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
XRES__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
XRES__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
XRES__SLW EQU CYREG_PRT12_SLW

; RxDMA
RxDMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
RxDMA__DRQ_NUMBER EQU 3
RxDMA__NUMBEROF_TDS EQU 0
RxDMA__PRIORITY EQU 0
RxDMA__TERMIN_EN EQU 0
RxDMA__TERMIN_SEL EQU 0
RxDMA__TERMOUT0_EN EQU 1
RxDMA__TERMOUT0_SEL EQU 3
RxDMA__TERMOUT1_EN EQU 0
RxDMA__TERMOUT1_SEL EQU 0

; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_arb_int__INTC_MASK EQU 0x400000
USBFS_arb_int__INTC_NUMBER EQU 22
USBFS_arb_int__INTC_PRIOR_NUM EQU 0
USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_bus_reset
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_bus_reset__INTC_MASK EQU 0x800000
USBFS_bus_reset__INTC_NUMBER EQU 23
USBFS_bus_reset__INTC_PRIOR_NUM EQU 5
USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_Dm
USBFS_Dm__0__MASK EQU 0x80
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBFS_Dm__0__PORT EQU 15
USBFS_Dm__0__SHIFT EQU 7
USBFS_Dm__AG EQU CYREG_PRT15_AG
USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
USBFS_Dm__BIE EQU CYREG_PRT15_BIE
USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
USBFS_Dm__BYP EQU CYREG_PRT15_BYP
USBFS_Dm__CTL EQU CYREG_PRT15_CTL
USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
USBFS_Dm__DR EQU CYREG_PRT15_DR
USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dm__MASK EQU 0x80
USBFS_Dm__PORT EQU 15
USBFS_Dm__PRT EQU CYREG_PRT15_PRT
USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
USBFS_Dm__PS EQU CYREG_PRT15_PS
USBFS_Dm__SHIFT EQU 7
USBFS_Dm__SLW EQU CYREG_PRT15_SLW

; USBFS_Dp
USBFS_Dp__0__MASK EQU 0x40
USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBFS_Dp__0__PORT EQU 15
USBFS_Dp__0__SHIFT EQU 6
USBFS_Dp__AG EQU CYREG_PRT15_AG
USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
USBFS_Dp__BIE EQU CYREG_PRT15_BIE
USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
USBFS_Dp__BYP EQU CYREG_PRT15_BYP
USBFS_Dp__CTL EQU CYREG_PRT15_CTL
USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
USBFS_Dp__DR EQU CYREG_PRT15_DR
USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dp__MASK EQU 0x40
USBFS_Dp__PORT EQU 15
USBFS_Dp__PRT EQU CYREG_PRT15_PRT
USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
USBFS_Dp__PS EQU CYREG_PRT15_PS
USBFS_Dp__SHIFT EQU 6
USBFS_Dp__SLW EQU CYREG_PRT15_SLW
USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15

; USBFS_dp_int
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_dp_int__INTC_MASK EQU 0x1000
USBFS_dp_int__INTC_NUMBER EQU 12
USBFS_dp_int__INTC_PRIOR_NUM EQU 5
USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_0
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_0__INTC_MASK EQU 0x1000000
USBFS_ep_0__INTC_NUMBER EQU 24
USBFS_ep_0__INTC_PRIOR_NUM EQU 4
USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_1
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_1__INTC_MASK EQU 0x08
USBFS_ep_1__INTC_NUMBER EQU 3
USBFS_ep_1__INTC_PRIOR_NUM EQU 4
USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_2
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_2__INTC_MASK EQU 0x10
USBFS_ep_2__INTC_NUMBER EQU 4
USBFS_ep_2__INTC_PRIOR_NUM EQU 4
USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_3
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_3__INTC_MASK EQU 0x20
USBFS_ep_3__INTC_NUMBER EQU 5
USBFS_ep_3__INTC_PRIOR_NUM EQU 2
USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_5
USBFS_ep_5__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_5__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_5__INTC_MASK EQU 0x80
USBFS_ep_5__INTC_NUMBER EQU 7
USBFS_ep_5__INTC_PRIOR_NUM EQU 4
USBFS_ep_5__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBFS_ep_5__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_5__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_6
USBFS_ep_6__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_6__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_6__INTC_MASK EQU 0x100
USBFS_ep_6__INTC_NUMBER EQU 8
USBFS_ep_6__INTC_PRIOR_NUM EQU 5
USBFS_ep_6__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
USBFS_ep_6__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_6__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_7
USBFS_ep_7__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_7__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_7__INTC_MASK EQU 0x200
USBFS_ep_7__INTC_NUMBER EQU 9
USBFS_ep_7__INTC_PRIOR_NUM EQU 6
USBFS_ep_7__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
USBFS_ep_7__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_7__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep_8
USBFS_ep_8__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_8__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ep_8__INTC_MASK EQU 0x400
USBFS_ep_8__INTC_NUMBER EQU 10
USBFS_ep_8__INTC_PRIOR_NUM EQU 4
USBFS_ep_8__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
USBFS_ep_8__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_8__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_EP_DMA_Done_isr
USBFS_EP_DMA_Done_isr__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_EP_DMA_Done_isr__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_EP_DMA_Done_isr__INTC_MASK EQU 0x04
USBFS_EP_DMA_Done_isr__INTC_NUMBER EQU 2
USBFS_EP_DMA_Done_isr__INTC_PRIOR_NUM EQU 0
USBFS_EP_DMA_Done_isr__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
USBFS_EP_DMA_Done_isr__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_EP_DMA_Done_isr__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_ep1
USBFS_ep1__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
USBFS_ep1__DRQ_NUMBER EQU 0
USBFS_ep1__NUMBEROF_TDS EQU 0
USBFS_ep1__PRIORITY EQU 2
USBFS_ep1__TERMIN_EN EQU 1
USBFS_ep1__TERMIN_SEL EQU 0
USBFS_ep1__TERMOUT0_EN EQU 1
USBFS_ep1__TERMOUT0_SEL EQU 0
USBFS_ep1__TERMOUT1_EN EQU 0
USBFS_ep1__TERMOUT1_SEL EQU 0

; USBFS_EP17_DMA_Done_SR
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__0__MASK EQU 0x01
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__0__POS EQU 0
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__1__MASK EQU 0x02
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__1__POS EQU 1
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__2__MASK EQU 0x04
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__2__POS EQU 2
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__3__MASK EQU 0x08
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__3__POS EQU 3
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__4__MASK EQU 0x10
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__4__POS EQU 4
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__5__MASK EQU 0x20
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__5__POS EQU 5
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__6__MASK EQU 0x40
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__6__POS EQU 6
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__MASK EQU 0x7F
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
USBFS_EP17_DMA_Done_SR_sts_intr_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST

; USBFS_ep2
USBFS_ep2__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
USBFS_ep2__DRQ_NUMBER EQU 1
USBFS_ep2__NUMBEROF_TDS EQU 0
USBFS_ep2__PRIORITY EQU 2
USBFS_ep2__TERMIN_EN EQU 1
USBFS_ep2__TERMIN_SEL EQU 0
USBFS_ep2__TERMOUT0_EN EQU 1
USBFS_ep2__TERMOUT0_SEL EQU 1
USBFS_ep2__TERMOUT1_EN EQU 0
USBFS_ep2__TERMOUT1_SEL EQU 0

; USBFS_ep3
USBFS_ep3__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
USBFS_ep3__DRQ_NUMBER EQU 2
USBFS_ep3__NUMBEROF_TDS EQU 0
USBFS_ep3__PRIORITY EQU 2
USBFS_ep3__TERMIN_EN EQU 1
USBFS_ep3__TERMIN_SEL EQU 0
USBFS_ep3__TERMOUT0_EN EQU 1
USBFS_ep3__TERMOUT0_SEL EQU 2
USBFS_ep3__TERMOUT1_EN EQU 0
USBFS_ep3__TERMOUT1_SEL EQU 0

; USBFS_ep5
USBFS_ep5__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
USBFS_ep5__DRQ_NUMBER EQU 4
USBFS_ep5__NUMBEROF_TDS EQU 0
USBFS_ep5__PRIORITY EQU 2
USBFS_ep5__TERMIN_EN EQU 1
USBFS_ep5__TERMIN_SEL EQU 0
USBFS_ep5__TERMOUT0_EN EQU 1
USBFS_ep5__TERMOUT0_SEL EQU 4
USBFS_ep5__TERMOUT1_EN EQU 0
USBFS_ep5__TERMOUT1_SEL EQU 0

; USBFS_ep6
USBFS_ep6__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
USBFS_ep6__DRQ_NUMBER EQU 5
USBFS_ep6__NUMBEROF_TDS EQU 0
USBFS_ep6__PRIORITY EQU 2
USBFS_ep6__TERMIN_EN EQU 1
USBFS_ep6__TERMIN_SEL EQU 0
USBFS_ep6__TERMOUT0_EN EQU 1
USBFS_ep6__TERMOUT0_SEL EQU 5
USBFS_ep6__TERMOUT1_EN EQU 0
USBFS_ep6__TERMOUT1_SEL EQU 0

; USBFS_ep7
USBFS_ep7__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
USBFS_ep7__DRQ_NUMBER EQU 6
USBFS_ep7__NUMBEROF_TDS EQU 0
USBFS_ep7__PRIORITY EQU 2
USBFS_ep7__TERMIN_EN EQU 1
USBFS_ep7__TERMIN_SEL EQU 0
USBFS_ep7__TERMOUT0_EN EQU 1
USBFS_ep7__TERMOUT0_SEL EQU 6
USBFS_ep7__TERMOUT1_EN EQU 0
USBFS_ep7__TERMOUT1_SEL EQU 0

; USBFS_ep8
USBFS_ep8__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
USBFS_ep8__DRQ_NUMBER EQU 7
USBFS_ep8__NUMBEROF_TDS EQU 0
USBFS_ep8__PRIORITY EQU 2
USBFS_ep8__TERMIN_EN EQU 1
USBFS_ep8__TERMIN_SEL EQU 0
USBFS_ep8__TERMOUT0_EN EQU 1
USBFS_ep8__TERMOUT0_SEL EQU 7
USBFS_ep8__TERMOUT1_EN EQU 0
USBFS_ep8__TERMOUT1_SEL EQU 0

; USBFS_EP8_DMA_Done_SR
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__0__MASK EQU 0x01
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__0__POS EQU 0
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__1__MASK EQU 0x02
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__1__POS EQU 1
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__MASK EQU 0x03
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
USBFS_EP8_DMA_Done_SR_sts_intr_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST

; USBFS_ord_int
USBFS_ord_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ord_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_ord_int__INTC_MASK EQU 0x2000000
USBFS_ord_int__INTC_NUMBER EQU 25
USBFS_ord_int__INTC_PRIOR_NUM EQU 5
USBFS_ord_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_25
USBFS_ord_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ord_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_sof_int
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_sof_int__INTC_MASK EQU 0x200000
USBFS_sof_int__INTC_NUMBER EQU 21
USBFS_sof_int__INTC_PRIOR_NUM EQU 5
USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; USBFS_USB
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
USBFS_USB__CR0 EQU CYREG_USB_CR0
USBFS_USB__CR1 EQU CYREG_USB_CR1
USBFS_USB__CWA EQU CYREG_USB_CWA
USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
USBFS_USB__PM_ACT_MSK EQU 0x01
USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
USBFS_USB__PM_STBY_MSK EQU 0x01
USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
USBFS_USB__SOF0 EQU CYREG_USB_SOF0
USBFS_USB__SOF1 EQU CYREG_USB_SOF1
USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1

; Clock_1
Clock_1__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
Clock_1__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
Clock_1__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
Clock_1__CFG2_SRC_SEL_MASK EQU 0x07
Clock_1__INDEX EQU 0x00
Clock_1__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
Clock_1__PM_ACT_MSK EQU 0x01
Clock_1__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
Clock_1__PM_STBY_MSK EQU 0x01

; USBInDMA
USBInDMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL2
USBInDMA__DRQ_NUMBER EQU 8
USBInDMA__NUMBEROF_TDS EQU 0
USBInDMA__PRIORITY EQU 3
USBInDMA__TERMIN_EN EQU 0
USBInDMA__TERMIN_SEL EQU 0
USBInDMA__TERMOUT0_EN EQU 1
USBInDMA__TERMOUT0_SEL EQU 8
USBInDMA__TERMOUT1_EN EQU 0
USBInDMA__TERMOUT1_SEL EQU 0

; Pin_UART_Rx
Pin_UART_Rx__0__MASK EQU 0x40
Pin_UART_Rx__0__PC EQU CYREG_PRT12_PC6
Pin_UART_Rx__0__PORT EQU 12
Pin_UART_Rx__0__SHIFT EQU 6
Pin_UART_Rx__AG EQU CYREG_PRT12_AG
Pin_UART_Rx__BIE EQU CYREG_PRT12_BIE
Pin_UART_Rx__BIT_MASK EQU CYREG_PRT12_BIT_MASK
Pin_UART_Rx__BYP EQU CYREG_PRT12_BYP
Pin_UART_Rx__DM0 EQU CYREG_PRT12_DM0
Pin_UART_Rx__DM1 EQU CYREG_PRT12_DM1
Pin_UART_Rx__DM2 EQU CYREG_PRT12_DM2
Pin_UART_Rx__DR EQU CYREG_PRT12_DR
Pin_UART_Rx__INP_DIS EQU CYREG_PRT12_INP_DIS
Pin_UART_Rx__MASK EQU 0x40
Pin_UART_Rx__PORT EQU 12
Pin_UART_Rx__PRT EQU CYREG_PRT12_PRT
Pin_UART_Rx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
Pin_UART_Rx__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
Pin_UART_Rx__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
Pin_UART_Rx__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
Pin_UART_Rx__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
Pin_UART_Rx__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
Pin_UART_Rx__PS EQU CYREG_PRT12_PS
Pin_UART_Rx__SHIFT EQU 6
Pin_UART_Rx__SIO_CFG EQU CYREG_PRT12_SIO_CFG
Pin_UART_Rx__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
Pin_UART_Rx__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
Pin_UART_Rx__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
Pin_UART_Rx__SLW EQU CYREG_PRT12_SLW

; Pin_UART_Tx
Pin_UART_Tx__0__MASK EQU 0x80
Pin_UART_Tx__0__PC EQU CYREG_PRT12_PC7
Pin_UART_Tx__0__PORT EQU 12
Pin_UART_Tx__0__SHIFT EQU 7
Pin_UART_Tx__AG EQU CYREG_PRT12_AG
Pin_UART_Tx__BIE EQU CYREG_PRT12_BIE
Pin_UART_Tx__BIT_MASK EQU CYREG_PRT12_BIT_MASK
Pin_UART_Tx__BYP EQU CYREG_PRT12_BYP
Pin_UART_Tx__DM0 EQU CYREG_PRT12_DM0
Pin_UART_Tx__DM1 EQU CYREG_PRT12_DM1
Pin_UART_Tx__DM2 EQU CYREG_PRT12_DM2
Pin_UART_Tx__DR EQU CYREG_PRT12_DR
Pin_UART_Tx__INP_DIS EQU CYREG_PRT12_INP_DIS
Pin_UART_Tx__MASK EQU 0x80
Pin_UART_Tx__PORT EQU 12
Pin_UART_Tx__PRT EQU CYREG_PRT12_PRT
Pin_UART_Tx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
Pin_UART_Tx__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
Pin_UART_Tx__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
Pin_UART_Tx__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
Pin_UART_Tx__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
Pin_UART_Tx__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
Pin_UART_Tx__PS EQU CYREG_PRT12_PS
Pin_UART_Tx__SHIFT EQU 7
Pin_UART_Tx__SIO_CFG EQU CYREG_PRT12_SIO_CFG
Pin_UART_Tx__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
Pin_UART_Tx__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
Pin_UART_Tx__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
Pin_UART_Tx__SLW EQU CYREG_PRT12_SLW

; Pin_PowerLED
Pin_PowerLED__0__MASK EQU 0x20
Pin_PowerLED__0__PC EQU CYREG_PRT1_PC5
Pin_PowerLED__0__PORT EQU 1
Pin_PowerLED__0__SHIFT EQU 5
Pin_PowerLED__AG EQU CYREG_PRT1_AG
Pin_PowerLED__AMUX EQU CYREG_PRT1_AMUX
Pin_PowerLED__BIE EQU CYREG_PRT1_BIE
Pin_PowerLED__BIT_MASK EQU CYREG_PRT1_BIT_MASK
Pin_PowerLED__BYP EQU CYREG_PRT1_BYP
Pin_PowerLED__CTL EQU CYREG_PRT1_CTL
Pin_PowerLED__DM0 EQU CYREG_PRT1_DM0
Pin_PowerLED__DM1 EQU CYREG_PRT1_DM1
Pin_PowerLED__DM2 EQU CYREG_PRT1_DM2
Pin_PowerLED__DR EQU CYREG_PRT1_DR
Pin_PowerLED__INP_DIS EQU CYREG_PRT1_INP_DIS
Pin_PowerLED__LCD_COM_SEG EQU CYREG_PRT1_LCD_COM_SEG
Pin_PowerLED__LCD_EN EQU CYREG_PRT1_LCD_EN
Pin_PowerLED__MASK EQU 0x20
Pin_PowerLED__PORT EQU 1
Pin_PowerLED__PRT EQU CYREG_PRT1_PRT
Pin_PowerLED__PRTDSI__CAPS_SEL EQU CYREG_PRT1_CAPS_SEL
Pin_PowerLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT1_DBL_SYNC_IN
Pin_PowerLED__PRTDSI__OE_SEL0 EQU CYREG_PRT1_OE_SEL0
Pin_PowerLED__PRTDSI__OE_SEL1 EQU CYREG_PRT1_OE_SEL1
Pin_PowerLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT1_OUT_SEL0
Pin_PowerLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT1_OUT_SEL1
Pin_PowerLED__PRTDSI__SYNC_OUT EQU CYREG_PRT1_SYNC_OUT
Pin_PowerLED__PS EQU CYREG_PRT1_PS
Pin_PowerLED__SHIFT EQU 5
Pin_PowerLED__SLW EQU CYREG_PRT1_SLW

; Pin_BLE_Extra
Pin_BLE_Extra__0__MASK EQU 0x10
Pin_BLE_Extra__0__PC EQU CYREG_IO_PC_PRT15_PC4
Pin_BLE_Extra__0__PORT EQU 15
Pin_BLE_Extra__0__SHIFT EQU 4
Pin_BLE_Extra__AG EQU CYREG_PRT15_AG
Pin_BLE_Extra__AMUX EQU CYREG_PRT15_AMUX
Pin_BLE_Extra__BIE EQU CYREG_PRT15_BIE
Pin_BLE_Extra__BIT_MASK EQU CYREG_PRT15_BIT_MASK
Pin_BLE_Extra__BYP EQU CYREG_PRT15_BYP
Pin_BLE_Extra__CTL EQU CYREG_PRT15_CTL
Pin_BLE_Extra__DM0 EQU CYREG_PRT15_DM0
Pin_BLE_Extra__DM1 EQU CYREG_PRT15_DM1
Pin_BLE_Extra__DM2 EQU CYREG_PRT15_DM2
Pin_BLE_Extra__DR EQU CYREG_PRT15_DR
Pin_BLE_Extra__INP_DIS EQU CYREG_PRT15_INP_DIS
Pin_BLE_Extra__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
Pin_BLE_Extra__LCD_EN EQU CYREG_PRT15_LCD_EN
Pin_BLE_Extra__MASK EQU 0x10
Pin_BLE_Extra__PORT EQU 15
Pin_BLE_Extra__PRT EQU CYREG_PRT15_PRT
Pin_BLE_Extra__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
Pin_BLE_Extra__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
Pin_BLE_Extra__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
Pin_BLE_Extra__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
Pin_BLE_Extra__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
Pin_BLE_Extra__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
Pin_BLE_Extra__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
Pin_BLE_Extra__PS EQU CYREG_PRT15_PS
Pin_BLE_Extra__SHIFT EQU 4
Pin_BLE_Extra__SLW EQU CYREG_PRT15_SLW

; Pin_StatusLED
Pin_StatusLED__0__MASK EQU 0x02
Pin_StatusLED__0__PC EQU CYREG_PRT3_PC1
Pin_StatusLED__0__PORT EQU 3
Pin_StatusLED__0__SHIFT EQU 1
Pin_StatusLED__AG EQU CYREG_PRT3_AG
Pin_StatusLED__AMUX EQU CYREG_PRT3_AMUX
Pin_StatusLED__BIE EQU CYREG_PRT3_BIE
Pin_StatusLED__BIT_MASK EQU CYREG_PRT3_BIT_MASK
Pin_StatusLED__BYP EQU CYREG_PRT3_BYP
Pin_StatusLED__CTL EQU CYREG_PRT3_CTL
Pin_StatusLED__DM0 EQU CYREG_PRT3_DM0
Pin_StatusLED__DM1 EQU CYREG_PRT3_DM1
Pin_StatusLED__DM2 EQU CYREG_PRT3_DM2
Pin_StatusLED__DR EQU CYREG_PRT3_DR
Pin_StatusLED__INP_DIS EQU CYREG_PRT3_INP_DIS
Pin_StatusLED__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
Pin_StatusLED__LCD_EN EQU CYREG_PRT3_LCD_EN
Pin_StatusLED__MASK EQU 0x02
Pin_StatusLED__PORT EQU 3
Pin_StatusLED__PRT EQU CYREG_PRT3_PRT
Pin_StatusLED__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
Pin_StatusLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
Pin_StatusLED__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
Pin_StatusLED__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
Pin_StatusLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
Pin_StatusLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
Pin_StatusLED__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
Pin_StatusLED__PS EQU CYREG_PRT3_PS
Pin_StatusLED__SHIFT EQU 1
Pin_StatusLED__SLW EQU CYREG_PRT3_SLW

; isr_InDMADone
isr_InDMADone__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
isr_InDMADone__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
isr_InDMADone__INTC_MASK EQU 0x800
isr_InDMADone__INTC_NUMBER EQU 11
isr_InDMADone__INTC_PRIOR_NUM EQU 2
isr_InDMADone__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11
isr_InDMADone__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
isr_InDMADone__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; isr_RxDMADone
isr_RxDMADone__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
isr_RxDMADone__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
isr_RxDMADone__INTC_MASK EQU 0x2000
isr_RxDMADone__INTC_NUMBER EQU 13
isr_RxDMADone__INTC_PRIOR_NUM EQU 3
isr_RxDMADone__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_13
isr_RxDMADone__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
isr_RxDMADone__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; isr_PktDecoder
isr_PktDecoder__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
isr_PktDecoder__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
isr_PktDecoder__INTC_MASK EQU 0x20000
isr_PktDecoder__INTC_NUMBER EQU 17
isr_PktDecoder__INTC_PRIOR_NUM EQU 7
isr_PktDecoder__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_17
isr_PktDecoder__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
isr_PktDecoder__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; isr_UsbSuspend
isr_UsbSuspend__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
isr_UsbSuspend__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
isr_UsbSuspend__INTC_MASK EQU 0x40000
isr_UsbSuspend__INTC_NUMBER EQU 18
isr_UsbSuspend__INTC_PRIOR_NUM EQU 7
isr_UsbSuspend__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_18
isr_UsbSuspend__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
isr_UsbSuspend__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; Clock_PktDecoder
Clock_PktDecoder__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
Clock_PktDecoder__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
Clock_PktDecoder__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
Clock_PktDecoder__CFG2_SRC_SEL_MASK EQU 0x07
Clock_PktDecoder__INDEX EQU 0x02
Clock_PktDecoder__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
Clock_PktDecoder__PM_ACT_MSK EQU 0x04
Clock_PktDecoder__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
Clock_PktDecoder__PM_STBY_MSK EQU 0x04

; Clock_UsbSuspend
Clock_UsbSuspend__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
Clock_UsbSuspend__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
Clock_UsbSuspend__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
Clock_UsbSuspend__CFG2_SRC_SEL_MASK EQU 0x07
Clock_UsbSuspend__INDEX EQU 0x01
Clock_UsbSuspend__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
Clock_UsbSuspend__PM_ACT_MSK EQU 0x02
Clock_UsbSuspend__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
Clock_UsbSuspend__PM_STBY_MSK EQU 0x02

; Pin_RemoteWakeup
Pin_RemoteWakeup__0__MASK EQU 0x20
Pin_RemoteWakeup__0__PC EQU CYREG_PRT2_PC5
Pin_RemoteWakeup__0__PORT EQU 2
Pin_RemoteWakeup__0__SHIFT EQU 5
Pin_RemoteWakeup__AG EQU CYREG_PRT2_AG
Pin_RemoteWakeup__AMUX EQU CYREG_PRT2_AMUX
Pin_RemoteWakeup__BIE EQU CYREG_PRT2_BIE
Pin_RemoteWakeup__BIT_MASK EQU CYREG_PRT2_BIT_MASK
Pin_RemoteWakeup__BYP EQU CYREG_PRT2_BYP
Pin_RemoteWakeup__CTL EQU CYREG_PRT2_CTL
Pin_RemoteWakeup__DM0 EQU CYREG_PRT2_DM0
Pin_RemoteWakeup__DM1 EQU CYREG_PRT2_DM1
Pin_RemoteWakeup__DM2 EQU CYREG_PRT2_DM2
Pin_RemoteWakeup__DR EQU CYREG_PRT2_DR
Pin_RemoteWakeup__INP_DIS EQU CYREG_PRT2_INP_DIS
Pin_RemoteWakeup__INTSTAT EQU CYREG_PICU2_INTSTAT
Pin_RemoteWakeup__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
Pin_RemoteWakeup__LCD_EN EQU CYREG_PRT2_LCD_EN
Pin_RemoteWakeup__MASK EQU 0x20
Pin_RemoteWakeup__PORT EQU 2
Pin_RemoteWakeup__PRT EQU CYREG_PRT2_PRT
Pin_RemoteWakeup__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
Pin_RemoteWakeup__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
Pin_RemoteWakeup__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
Pin_RemoteWakeup__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
Pin_RemoteWakeup__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
Pin_RemoteWakeup__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
Pin_RemoteWakeup__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
Pin_RemoteWakeup__PS EQU CYREG_PRT2_PS
Pin_RemoteWakeup__SHIFT EQU 5
Pin_RemoteWakeup__SLW EQU CYREG_PRT2_SLW
Pin_RemoteWakeup__SNAP EQU CYREG_PICU2_SNAP

; Timer_PktDecoder_TimerHW
Timer_PktDecoder_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
Timer_PktDecoder_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
Timer_PktDecoder_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
Timer_PktDecoder_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
Timer_PktDecoder_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
Timer_PktDecoder_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
Timer_PktDecoder_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
Timer_PktDecoder_TimerHW__PER0 EQU CYREG_TMR0_PER0
Timer_PktDecoder_TimerHW__PER1 EQU CYREG_TMR0_PER1
Timer_PktDecoder_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
Timer_PktDecoder_TimerHW__PM_ACT_MSK EQU 0x01
Timer_PktDecoder_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
Timer_PktDecoder_TimerHW__PM_STBY_MSK EQU 0x01
Timer_PktDecoder_TimerHW__RT0 EQU CYREG_TMR0_RT0
Timer_PktDecoder_TimerHW__RT1 EQU CYREG_TMR0_RT1
Timer_PktDecoder_TimerHW__SR0 EQU CYREG_TMR0_SR0

; Timer_UsbSuspend_Reset
Timer_UsbSuspend_Reset_Sync_ctrl_reg__0__MASK EQU 0x01
Timer_UsbSuspend_Reset_Sync_ctrl_reg__0__POS EQU 0
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
Timer_UsbSuspend_Reset_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__MASK EQU 0x01
Timer_UsbSuspend_Reset_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
Timer_UsbSuspend_Reset_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK

; Timer_UsbSuspend_TimerHW
Timer_UsbSuspend_TimerHW__CAP0 EQU CYREG_TMR1_CAP0
Timer_UsbSuspend_TimerHW__CAP1 EQU CYREG_TMR1_CAP1
Timer_UsbSuspend_TimerHW__CFG0 EQU CYREG_TMR1_CFG0
Timer_UsbSuspend_TimerHW__CFG1 EQU CYREG_TMR1_CFG1
Timer_UsbSuspend_TimerHW__CFG2 EQU CYREG_TMR1_CFG2
Timer_UsbSuspend_TimerHW__CNT_CMP0 EQU CYREG_TMR1_CNT_CMP0
Timer_UsbSuspend_TimerHW__CNT_CMP1 EQU CYREG_TMR1_CNT_CMP1
Timer_UsbSuspend_TimerHW__PER0 EQU CYREG_TMR1_PER0
Timer_UsbSuspend_TimerHW__PER1 EQU CYREG_TMR1_PER1
Timer_UsbSuspend_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
Timer_UsbSuspend_TimerHW__PM_ACT_MSK EQU 0x02
Timer_UsbSuspend_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
Timer_UsbSuspend_TimerHW__PM_STBY_MSK EQU 0x02
Timer_UsbSuspend_TimerHW__RT0 EQU CYREG_TMR1_RT0
Timer_UsbSuspend_TimerHW__RT1 EQU CYREG_TMR1_RT1
Timer_UsbSuspend_TimerHW__SR0 EQU CYREG_TMR1_SR0

; isr_RemoteWakeup
isr_RemoteWakeup__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
isr_RemoteWakeup__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
isr_RemoteWakeup__INTC_MASK EQU 0x40
isr_RemoteWakeup__INTC_NUMBER EQU 6
isr_RemoteWakeup__INTC_PRIOR_NUM EQU 7
isr_RemoteWakeup__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
isr_RemoteWakeup__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
isr_RemoteWakeup__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0

; Miscellaneous
BCLK__BUS_CLK__HZ EQU 66000000
BCLK__BUS_CLK__KHZ EQU 66000
BCLK__BUS_CLK__MHZ EQU 66
CYDEV_CHIP_DIE_GEN4 EQU 2
CYDEV_CHIP_DIE_LEOPARD EQU 1
CYDEV_CHIP_DIE_PANTHER EQU 13
CYDEV_CHIP_DIE_PSOC4A EQU 6
CYDEV_CHIP_DIE_PSOC5LP EQU 12
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E127069
CYDEV_CHIP_MEMBER_3A EQU 1
CYDEV_CHIP_MEMBER_4A EQU 6
CYDEV_CHIP_MEMBER_4C EQU 10
CYDEV_CHIP_MEMBER_4D EQU 3
CYDEV_CHIP_MEMBER_4E EQU 5
CYDEV_CHIP_MEMBER_4F EQU 7
CYDEV_CHIP_MEMBER_4G EQU 2
CYDEV_CHIP_MEMBER_4H EQU 4
CYDEV_CHIP_MEMBER_4L EQU 9
CYDEV_CHIP_MEMBER_4M EQU 8
CYDEV_CHIP_MEMBER_5A EQU 12
CYDEV_CHIP_MEMBER_5B EQU 11
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_REV_GEN4_ES EQU 17
CYDEV_CHIP_REV_GEN4_ES2 EQU 33
CYDEV_CHIP_REV_GEN4_PRODUCTION EQU 17
CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
CYDEV_CHIP_REVISION_4G_ES EQU 17
CYDEV_CHIP_REVISION_4G_ES2 EQU 33
CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_Disable
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x80
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00002807
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
CYDEV_STACK_SIZE EQU 0x0800
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDA_MV EQU 5000
CYDEV_VDDD_MV EQU 5000
CYDEV_VDDIO0_MV EQU 5000
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
CYDEV_VIO0_MV EQU 5000
CYDEV_VIO1_MV EQU 5000
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3_MV EQU 5000
CYIPBLOCK_ARM_CM3_VERSION EQU 0
CYIPBLOCK_P3_ANAIF_VERSION EQU 0
CYIPBLOCK_P3_CAN_VERSION EQU 0
CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
CYIPBLOCK_P3_COMP_VERSION EQU 0
CYIPBLOCK_P3_DECIMATOR_VERSION EQU 0
CYIPBLOCK_P3_DFB_VERSION EQU 0
CYIPBLOCK_P3_DMA_VERSION EQU 0
CYIPBLOCK_P3_DRQ_VERSION EQU 0
CYIPBLOCK_P3_DSM_VERSION EQU 0
CYIPBLOCK_P3_EMIF_VERSION EQU 0
CYIPBLOCK_P3_I2C_VERSION EQU 0
CYIPBLOCK_P3_LCD_VERSION EQU 0
CYIPBLOCK_P3_LPF_VERSION EQU 0
CYIPBLOCK_P3_OPAMP_VERSION EQU 0
CYIPBLOCK_P3_PM_VERSION EQU 0
CYIPBLOCK_P3_SCCT_VERSION EQU 0
CYIPBLOCK_P3_TIMER_VERSION EQU 0
CYIPBLOCK_P3_USB_VERSION EQU 0
CYIPBLOCK_P3_VIDAC_VERSION EQU 0
CYIPBLOCK_P3_VREF_VERSION EQU 0
CYIPBLOCK_S8_GPIO_VERSION EQU 0
CYIPBLOCK_S8_IRQ_VERSION EQU 0
CYIPBLOCK_S8_SAR_VERSION EQU 0
CYIPBLOCK_S8_SIO_VERSION EQU 0
CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x000001FF
CYDEV_BOOTLOADER_ENABLE EQU 0
    ENDIF
    END
